Many processing systems, whether simple or complex, use data buses to transfer data between components. One common data bus configuration is a peripheral component interconnect (PCI) data bus. These inexpensive buses are often used to transfer data, for example, between a processor and an external memory, or between a data capture device and a processor. Depending on the desired configuration, different devices may act as a PCI master and write the data on the PCI bus for reception at a device operating as a PCI slave device.
In some common configurations, the processor is configured as a PCI master and reads data from a data capture device, and writes data to a memory device, such as a hard disc. However, due to the operation of the PCI buses, when data is read from a device by a PCI master, the data may be delayed due to the target device when it is not ready to transfer data. This results in delays in the data transfer and may affect system performance.